1 // Copyright 2018 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
5 // Package cpu implements processor feature detection for
6 // various CPU architectures.
9 // Initialized reports whether the CPU features were initialized.
11 // For some GOOS/GOARCH combinations initialization of the CPU features depends
12 // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
13 // Initialized will report false if reading the file fails.
16 // CacheLinePad is used to pad structs to avoid false sharing.
17 type CacheLinePad struct{ _ [cacheLineSize]byte }
19 // X86 contains the supported CPU features of the
20 // current X86/AMD64 platform. If the current platform
21 // is not X86/AMD64 then all feature flags are false.
23 // X86 is padded to avoid false sharing. Further the HasAVX
24 // and HasAVX2 are only set if the OS supports XMM and YMM
25 // registers in addition to the CPUID feature bit being set.
28 HasAES bool // AES hardware implementation (AES NI)
29 HasADX bool // Multi-precision add-carry instruction extensions
30 HasAVX bool // Advanced vector extension
31 HasAVX2 bool // Advanced vector extension 2
32 HasBMI1 bool // Bit manipulation instruction set 1
33 HasBMI2 bool // Bit manipulation instruction set 2
34 HasERMS bool // Enhanced REP for MOVSB and STOSB
35 HasFMA bool // Fused-multiply-add instructions
36 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
37 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
38 HasPOPCNT bool // Hamming weight instruction POPCNT.
39 HasRDRAND bool // RDRAND instruction (on-chip random number generator)
40 HasRDSEED bool // RDSEED instruction (on-chip random number generator)
41 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
42 HasSSE3 bool // Streaming SIMD extension 3
43 HasSSSE3 bool // Supplemental streaming SIMD extension 3
44 HasSSE41 bool // Streaming SIMD extension 4 and 4.1
45 HasSSE42 bool // Streaming SIMD extension 4 and 4.2
49 // ARM64 contains the supported CPU features of the
50 // current ARMv8(aarch64) platform. If the current platform
51 // is not arm64 then all feature flags are false.
54 HasFP bool // Floating-point instruction set (always available)
55 HasASIMD bool // Advanced SIMD (always available)
56 HasEVTSTRM bool // Event stream support
57 HasAES bool // AES hardware implementation
58 HasPMULL bool // Polynomial multiplication instruction set
59 HasSHA1 bool // SHA1 hardware implementation
60 HasSHA2 bool // SHA2 hardware implementation
61 HasCRC32 bool // CRC32 hardware implementation
62 HasATOMICS bool // Atomic memory operation instruction set
63 HasFPHP bool // Half precision floating-point instruction set
64 HasASIMDHP bool // Advanced SIMD half precision instruction set
65 HasCPUID bool // CPUID identification scheme registers
66 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
67 HasJSCVT bool // Javascript conversion from floating-point to integer
68 HasFCMA bool // Floating-point multiplication and addition of complex numbers
69 HasLRCPC bool // Release Consistent processor consistent support
70 HasDCPOP bool // Persistent memory support
71 HasSHA3 bool // SHA3 hardware implementation
72 HasSM3 bool // SM3 hardware implementation
73 HasSM4 bool // SM4 hardware implementation
74 HasASIMDDP bool // Advanced SIMD double precision instruction set
75 HasSHA512 bool // SHA512 hardware implementation
76 HasSVE bool // Scalable Vector Extensions
77 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
81 // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
82 // If the current platform is not ppc64/ppc64le then all feature flags are false.
84 // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
85 // since there are no optional categories. There are some exceptions that also
86 // require kernel support to work (DARN, SCV), so there are feature bits for
87 // those as well. The minimum processor requirement is POWER8 (ISA 2.07).
88 // The struct is padded to avoid false sharing.
91 HasDARN bool // Hardware random number generator (requires kernel enablement)
92 HasSCV bool // Syscall vectored (requires kernel enablement)
93 IsPOWER8 bool // ISA v2.07 (POWER8)
94 IsPOWER9 bool // ISA v3.00 (POWER9)
98 // S390X contains the supported CPU features of the current IBM Z
99 // (s390x) platform. If the current platform is not IBM Z then all
100 // feature flags are false.
102 // S390X is padded to avoid false sharing. Further HasVX is only set
103 // if the OS supports vector registers in addition to the STFLE
104 // feature bit being set.
107 HasZARCH bool // z/Architecture mode is active [mandatory]
108 HasSTFLE bool // store facility list extended
109 HasLDISP bool // long (20-bit) displacements
110 HasEIMM bool // 32-bit immediates
111 HasDFP bool // decimal floating point
112 HasETF3EH bool // ETF-3 enhanced
113 HasMSA bool // message security assist (CPACF)
114 HasAES bool // KM-AES{128,192,256} functions
115 HasAESCBC bool // KMC-AES{128,192,256} functions
116 HasAESCTR bool // KMCTR-AES{128,192,256} functions
117 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
118 HasGHASH bool // KIMD-GHASH function
119 HasSHA1 bool // K{I,L}MD-SHA-1 functions
120 HasSHA256 bool // K{I,L}MD-SHA-256 functions
121 HasSHA512 bool // K{I,L}MD-SHA-512 functions
122 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
123 HasVX bool // vector facility
124 HasVXE bool // vector-enhancements facility 1